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integrated circuit systems, inc. ics9248-168 third party brands and names are the property of their respective owners. block diagram functionality pin configuration 48-pin 300mil ssop recommended application: via kt133 style chipset output features: ? 1 - differential pair open drain cpu clocks 1 - cpu clock @ 3.3v 7 - sdram @ 3.3v 8 - pci @ 3.3v, 1 - 48mhz, @ 3.3v fixed. 1 - 24/48mhz @ 3.3v 3 - ref @ 3.3v, 14.318mhz. features: up to 153mhz frequency support support power management: cpu stop and power down mode from i 2 c programming. spread spectrum for emi control ( 0.25% to 0.6% center, or 0 to -0.5% or -1.0% down spread). uses external 14.318mhz crystal amd - k7 ? clock generator for mobile system * internal pull-up resistor of 120k to vdd 1 these outputs have double strength to drive 2 loads. 2 these outputs can be set to 1.5x strength through i 2 c vddref x1 x2 *fs2/pciclk_f *fs1/pciclk0 vddpci gnd pciclk1 pciclk2 pciclk3 pciclk4 pciclk5 gnd vddpci pciclk6 *sdram_stop# *pci_stop# buffer_in avdd gnd gnd *fs0/48mhz *sel24_48#/24_48mhz vdd48 ref0 ref ref2 gnd gnd vdd cpuclk cpuclkt0 cpuclkc0 cpu_stop#* pd#* sdram0 sdram1 vddsdr gnd sdram2 sdram3 gnd vddsdr sdram4 sdram5 sdram_f sclk s data 1 2 2 2 1 ics9248-168 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2 s f1 s f0 s fu p ci c pe g a t n e c r e p d a e r p s 000 0 0 . 0 0 13 3 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 001 3 3 . 3 3 13 3 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 010 0 0 . 0 0 13 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 011 3 3 . 3 3 13 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 100 0 0 . 0 0 13 3 . 3 3d a e r p s r e t n e c % 6 . 0 - / + 10 1 3 3 . 3 3 13 3 . 3 3d a e r p s r e t n e c % 6 . 0 - / + 110 0 0 . 0 90 0 . 0 3d a e r p s r e t n e c % 5 2 . 0 - / + 111 0 0 . 0 2 10 0 . 0 3d a e r p s r e t n e c % 5 2 . 0 - / + sel24_48# s data sclk fs (2:0) pd# cpu_stop# pci_stop# sdram_stop# buffer_in pll2 pll1 spread spectrum 48mhz 24_48mhz sdram (5:0) pciclk (6:0) pciclk_f sdram_f cpuclkt0 cpuclk cpuclkc0 x1 x2 xtal osc cpu divder pci divder stop stop stop control logic config. reg. / 2 ref (2:0) sdram driver ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 9248-168 rev b 01/09/01
2 ics9248-168 third party brands and names are the property of their respective owners. pin descriptions notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i p e m a n n i pe p y tn o i t p i r c s e d , 4 2 , 4 1 , 6 , 1 3 4 , 5 3 , 0 3 d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p 2 1 xn i k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 3 2 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 6 3 ( p a c 4 2 s f 2 , 1 n id d v o t p u - l l u p l a n r e t n i . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f f _ k l c i c pt u o r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f . t n e m e g a n a m 5 1 s f 2 , 1 n id d v o t p u - l l u p l a n r e t n i . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u ot u p t u o k c o l c i c p , 4 3 , 1 3 , 1 2 , 0 2 , 3 1 , 7 5 4 , 4 4 d n gr w pd n u o r g 8 , 9 , 0 1 , 1 1 , 2 1 , 5 1 ) 1 : 6 ( k l c i c pt u o. s t u p t u o k c o l c i c p 6 1 # p o t s _ m a r d sn i , l e v e l 0 c i g o l t a s k c o l c f _ m a r d s e h t s e d i s e b s m a r d s l l a s p o t s w o l t u p n i n e h w 7 1# p o t s _ k l c i c pn i , l e v e l 0 c i g o l t a s k c o l c f _ k l c i c p e h t s e d i s e b s k l c i c p l l a s p o t s w o l t u p n i n e h w 8 1 n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i 9 1 d d v ar w pv 3 . 3 u p c & , e r o c r o f y l p p u s 2 2 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f z h m 8 4t u ok c o l c t u p t u o z h m 8 4 3 2 # 8 4 _ 4 2 l e s 2 , 1 n it u p t u o 5 2 n i p r o f z h m 8 4 r o 4 2 t c e l e s o t t u p n i c i g o l z h m 8 4 _ 4 2t u ot u p t u o k c o l c z h m 8 4 / z h m 4 2 5 2 a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 6 2k l c sn ii f o n i p k c o l c 2 t n a r e l o t v 5 y r t i u c r i c c 7 2 f _ m a r d st u o r o f # p o t s _ m a r d s y b d e t c e f f a t o n k c o l c m a r d s g n i n n u r e e r f . t n e m e g a n a m r e w o p 7 3 , 6 3 , 3 3 , 2 3 , 9 2 , 8 2 ) 0 : 5 ( m a r d st u o n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s . ) t e s p i h c y b d e l l o r t n o c ( 8 3 # d pn iw o l e v i t c a , p i h c n w o d s r e w o p 9 3 # p o t s _ u p c , 1 n i t a m a r d s & c k l c u p c , t k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t . w o l n e v i r d n e h w l e v e l " 0 " c i g o l 0 4 0 c k l c u p ct u o n e p o s i h t . t u p t u o u p c r i a p l a i t n e r e f f i d f o k c o l c " y r o t n e m e l p m o c " . p u - l l u p v 5 . 1 l a n r e t x e n a s d e e n s t u p t u o n i a r d 1 4 0 t k l c u p ct u o n i a r d n e p o e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . p u - l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o 2 4 k l c u p ct u oa d d v y b d e r e w o p t u p t u o k c o l c u p c v 3 . 3 8 4 , 7 4 , 6 4 ) 0 : 2 ( 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1
3 ics9248-168 third party brands and names are the property of their respective owners. general description the ics9248-168 is a main clock synthesizer chip for amd-k7 based note book systems with via style chipset. this provides all clocks required for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248-168 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. power groups vdd48 = 48mhz, fixed pll vdda = vdd for core pll vddref = ref, xtal
4 ics9248-168 third party brands and names are the property of their respective owners. byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note: default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i bn o i t p i r c s e dd w p , 2 t i b 4 : 7 t i b t i b 2 t i b 7 t i b 6 t i b 5 t i b 4 k l c u p c ) z h m ( k l c i c p ) z h m ( d a e r p s e g a t n e c e r p d e v r e s e r 1 0 1 0 0 00000 0 0 . 0 0 13 3 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 00001 3 3 . 3 3 13 3 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 00010 0 0 . 0 0 13 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 00011 3 3 . 3 3 13 3 . 3 3d a e r p s n w o d % 5 . 0 - o t 0 00100 0 0 . 0 0 13 3 . 3 3d a e r p s r e t n e c % 6 . 0 - / + 00101 3 3 . 3 3 13 3 . 3 3d a e r p s r e t n e c % 6 . 0 - / + 00110 0 0 . 0 90 0 . 0 3d a e r p s r e t n e c % 5 2 . 0 - / + 00111 0 0 . 0 2 10 0 . 0 3d a e r p s r e t n e c % 5 2 . 0 - / + 01000 0 3 . 0 0 13 4 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 01001 3 7 . 3 3 13 4 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 01010 0 3 . 0 0 13 4 . 3 3d a e r p s r e t n e c % 0 6 . 0 - / + 01011 3 7 . 3 3 13 4 . 3 3d a e r p s r e t n e c % 0 6 . 0 - / + 01100 0 0 . 1 0 17 6 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 01101 6 6 . 4 3 17 6 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 01110 0 0 . 2 0 10 0 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 01111 0 0 . 6 3 10 0 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10000 0 0 . 3 0 13 3 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10001 3 3 . 7 3 13 3 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 100 10 0 0 . 4 0 17 6 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 100 11 6 6 . 8 3 17 6 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 100 0 0 . 5 0 10 0 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 10 1 0 0 . 0 4 10 0 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 110 0 0 . 7 0 17 6 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 10111 6 6 . 2 4 17 6 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 11000 0 0 . 0 1 17 6 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 11001 6 6 . 6 4 17 6 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 11010 0 0 . 5 1 13 3 . 8 3d a e r p s r e t n e c % 5 3 . 0 - / + 11011 3 3 . 3 5 13 3 . 8 3d a e r p s r e t n e c % 5 3 . 0 - / + 11100 0 0 . 0 0 13 3 . 3 3d a e r p s r e t n e c % 0 5 . 0 - / + 11101 3 3 . 3 3 13 3 . 3 3d a e r p s r e t n e c % 0 5 . 0 - / + 11110 0 0 . 0 0 13 3 . 3 3d a e r p s n w o d % 0 . 1 - o t 0 11111 3 3 . 3 3 13 3 . 3 3d a e r p s n w o d % 0 . 1 - o t 0 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 2 . 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
5 ics9248-168 third party brands and names are the property of their respective owners. byte 1: cpu, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b2 210 s f 6 t i b511 s f 5 t i b412 s f 4 t i b2 41 x 1 = 1 x 5 . 1 = 0 k l c u p c 3 t i b-1 d e v r e s e r 2 t i b0 4 , 1 41 x 1 = 1 x 5 . 1 = 0 c / t k l c u p c 1 t i b-1 d e v r e s e r 0 t i b2 41 k l c u p c byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b41 f _ k l c i c p 6 t i b5 11 6 k l c i c p 5 t i b2 11 5 k l c i c p 4 t i b1 11 4 k l c i c p 3 t i b0 11 3 k l c i c p 2 t i b91 2 k l c i c p 1 t i b81 1 k l c i c p 0 t i b51 0 k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b7 21 f _ m a r d s 5 t i b8 21 5 m a r d s 4 t i b9 21 4 m a r d s 3 t i b2 31 3 m a r d s 2 t i b3 31 2 m a r d s 1 t i b6 31 1 m a r d s 0 t i b7 31 0 m a r d s byte 4: sdram , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r byte 5: peripheral , active/inactive register (1= enable, 0 = disable) byte 3: active/inactive register (1= enable, 0 = disable) byte 6: peripheral , active/inactive register (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b3 21 # 8 4 _ 4 2 l e s 5 t i b2 21 z h m 8 4 4 t i b3 21 z h m 8 4 _ 4 2 3 t i b8 410 f e r 2 t i b7 411 f e r 1 t i b6 412 f e r 0 t i b-1 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-0 d e v r e s e r
6 ics9248-168 third party brands and names are the property of their respective owners. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5 ua input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ua input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ua operating supply current i dd3.3op c l =20 pf; sdram not running 75 180 ma power down pd 280 600 ua input frequency f i v dd = 3.3 v 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew window 1 t cpu-pci window vt=50% cpu - 1.5v pci; cpu leads 250 500 ps 1 guaranteed by design, not 100% tested in production. input capacitance 1 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units out p ut im p edance 1 r dsp5b v o =v dd * ( 0.5 ) 20 24 60 ? out p ut im p edance 1 r dsn5b v o =v dd * ( 0.5 ) 20 44 60 ? output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 1 v ol = 0.4 v , v oh = 2.4 v 1.7 4.0 ns fall time 1 t f5 1 v oh = 2.4 v , v ol = 0.4 v 1.5 4.0 ns dut y c y cle 1 d t5 1 v t = 1.5 v 45 52.8 55 % jitter , c y cle-to-c y cle 1 t j c y c-c y c5 1 v t = 1.5 v 770 1000 ps 1 guaranteed b y desi g n , not 100% tested in p roduction.
7 ics9248-168 third party brands and names are the property of their respective owners. electrical characteristics - cpuclk (open drain) t a = 0 - 70c; v dd =3.3v +/- 5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance z o 1 v o =v x 60 ? output high voltage v oh2b termination to v p ull-u p( external ) 11.8v output low voltage v ol2b termination to v p ull-u p( external ) 0.8 v output low current i ol2b v ol = 0.3 v 18 ma rise time 1 t r2b 1 v oh = 1.2 v, v ol = 0.3v 0.5 0.9 ns f a ll tim e 1 t f2b 1 v ol = 0.3 v, v oh = 1.2v 0.3 0.9 ns differential volta g e-ac 1 v dif n ote 2 0.4 v p ull-u p( ext ) + 0.6 v differential volta g e-dc 1 v dif n ote 2 0.2 v p ull-u p( ext ) + 0.6 v diff crossover voltage 1 v x n ote 3 1.2 0.82 1.8 v dut y c y cle 1 d t2b 1 v t = 50% 45 51.5 55 % skew window 1 t sk2b 1 v t = 50% 200 p s jitter, c y cle-to-c y cle 1 t j c y c-c y c 2b 1 v t = v x 125 300 p s jitter, absolute 1 tjabs 2b 1 v t = 50% 250 ps notes: 1 - guaranteed by design, not 100% tested in production. 2 - v dif s p ecifies the minimum in p ut differential volta g es ( v tr -v cp ) re q uired for switchin g , where v tr is the "true" in p ut level and v cp is the "com p lement" in p ut level. 3 - v p ull-u p( external ) = 2.7v, min=v p ull-u p( external ) /2-150mv; max=v p ull-u p( external ) /2 +150mv electrical characteristics - cpuclk t a = 0 - 70c; v dd =3.3v +/- 5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12.0 ma 1 1.8 v output low voltage v ol2b i oh = 12.0 ma 0.8 v output low current i ol2b v ol = 1.7 v 18 ma output low current i ol2b v ol = 0.7 v 18 ma rise time 1 t r2b 1 v ol = 0.4 v, v ol = 2.0v 0.9 1.6 ns f a ll tim e 1 t f2b 1 v oh = 2.0 v, v ol = 0.4v 0.8 1.6 ns dut y c y cle 1 d t2b 1 v t = 1.5v 45 51.5 55 % skew window 1 t sk2b 1 v t = 1.5v 200 p s jitter, cycle-to-cycle 1 t j c y c-c y c 2b 1 v t = 1.5v 125 300 p s jitter, absolute 1 tjabs 2b 1 v t = 1.5v 250 ps notes: 1 - guaranteed b y desi g n, not 100% tested in p roduction.
8 ics9248-168 third party brands and names are the property of their respective owners. electrical characteristics - pciclk t a = 0 - 70c; v dd = v ddl = 3.3v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o =v dd * ( 0.5 ) 12 24 55 ? output impedance r dsn2b 1 v o =v dd * ( 0.5 ) 12 23 55 ? output high voltage v oh1 i oh = -11 ma 2.6 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -16 ma output low current i ol1 v ol = 0.8 v 19 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.29 2.5 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.29 2.5 ns dut y c y cle 1 d t1 v t = 1.5 v 45 50.2 55 % skew window 1 t sk1 v t = 1.5 v 280 400 p s jitter, cyc-to-cyc t jcyc-cyc1 v t = 1.5 v 86 200 ps 1 guaranteed b y desi g n , not 100% tested in p roduction. electrical characteristics - sdram_out t a = 0 - 70c; v dd =3.3v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp3 v o =v dd * ( 0.5 ) 10 11 24 ? output impedance 1 r dsn3 v o =v dd * ( 0.5 ) 10 12 24 ? output high voltage v oh3 i oh = -11 ma 2 v output low voltage v ol3 i ol = 11 ma 0.4 v output high current i oh3 v oh = 2.0 v -12 ma output low current i ol3 v ol = 0.8 v 12 ma rise time 1 t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.9 1.5 ns fall time 1 t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.8 1.5 ns dut y c y cle 1 d t3 1 v t = 1.5 v 45 51.5 55 % skew (ouput to output) 1 t sk3a v t = 1.5 v 220 250 p s skew (buffer in to output) 1 t sk3b v t = 1.5 v 3ns 1 guaranteed b y desi g n , not 100% tested in p roduction.
9 ics9248-168 third party brands and names are the property of their respective owners. electrical characteristics - pciclk_f t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp1b v o =v dd * ( 0.5 ) 12 14 55 ? output impedance 1 r dsn1b v o =v dd * ( 0.5 ) 12 13 55 ? output high voltage v oh1 i oh = -11 ma 2.6 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -12 ma output low current i ol1 v ol = 0.8 v 12 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.4 2.0 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.3 2.0 ns dut y c y cle 1 d t1 v t = 1.5 v 45 50.2 55 % skew window 1 t sk1 v t = 1.5 v 280 400 p s jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 200 ps 1 guaranteed b y desi g n , not 100% tested in p roduction. electrical characteristics - 24mhz, 48mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp5b v o =v dd * ( 0.5 ) 20 24 60 ? output impedance 1 r dsn5b v o =v dd * ( 0.5 ) 20 44 60 ? output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.8 4.0 ns fall time 1 t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.8 4.0 ns dut y c y cle 1 d t5 1 v t = 1.5 v 24 48 mhz 45 53 55 % jitter, c y cle-to-c y cle 1 t j c y c-c y c5 1 v t = 1.5 v 150 500 ps 1 guaranteed b y desi g n , not 100% tested in p roduction.
10 ics9248-168 third party brands and names are the property of their respective owners. 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
11 ics9248-168 third party brands and names are the property of their respective owners. fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 168 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
12 ics9248-168 third party brands and names are the property of their respective owners. pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. cpu_stop# is considered to be a don't care during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248-168 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclkt cpuclkc pciclk vco crystal pd#
13 ics9248-168 third party brands and names are the property of their respective owners. cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ics9248-168 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less th an 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ics9248-168. 3. all other clocks continue to run undisturbed.
14 ics9248-168 third party brands and names are the property of their respective owners. ordering information ics9248 y f-168-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min ma x min ma x a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min ma x min ma x 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 64 20.828 21.082 .820 .830 symbol see variations see variations in millimeters common dimensions in inc hes common dimensions see variations n d mm. d (inch) see variations ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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